Implementation aspects of ATM switches

Since in the future, the demand on broadband services (e.g. Lan and video interconnection services) is likely to increase, research is focusing on the introduction of the Broadband ISDN. In 1989 standards on the transfer mode for B-ISDN were introduced: ATM. From then a lot of ATM switch designs were introduced, but they all assume the VLSI technology to be more developed than it actually is. This report describes which modifications should be performed on the switch designs to make them better implementable. This includes a detailed examination of general ATM switch designs, an examination of Delta, Clos and Benes networks and an overview of actual introduced ATM switch designs. Since for complex circuits maximum on-chip frequency is currently limited to about 50MHz (off-chip 25MHz) and ATM traffic has a speed of 155Mbit/s or more, parallellisation has to be performed to be able to reduce speed. Bitparallellisation means a cell is divided in several bits wide packets. It has the advantages of having only a small speed adaptation buffer delay and of guaranteeing preservation of cell sequence integrity. Cellparallellisation means cells are divided over switch copies, which reduces the load per switch copy. This has the advantage of having more evenly spread traffic. Since large switch designs can't be put on one chip and because they have to be modular, they have to be partitioned. Slicing means the large switch design (with parallellisation) is cut in a way that one copy of a switch which results from the parallellisation, is kept in one piece, i.e. the switch is divided in planes. Slicing can only be performed after parallellisation is performed, and results in all equal parts. Logical partitioning means the switch design is cut in a way that one part is a part of an ASE, one ASE or several ASE's. Logical partitioning is needed when slicing on its own is not sufficient and leads to several bits wide parts. This might be all equal parts (depending on the design). How the partitioning should be performed depends on the switch design. Small ASE's (size 2x2 or 4x4) don't have to be partitioned themselves. The MIN's these ASE's are used in, are based on Delta networks. Of these networks, the Batcher-Banyan network should be logical partitioned in a way that one part is one stage of ASE's. The other small ASE based networks should be partitioned in a way that one part is a stage of larger (than 2x2) networks. Limited size ASE's are ASE's which can't grow beyond some size, because of limitations in technology. These ASE's should be sliced, to keep high (size dependable) speed links on-chip. Unlimited size ASE's can grow without meeting limitations in technology. Because of their large complexity and their regular design, they should be logical partitioned. Both limited size and unlimited size ASE's are used in folded and unfolded Clos and Benes networks. For Benes networks the unfolded network is preferred because it uses less chips. For the Clos networks, the folded network with all equal ASE' s is preferred, because although it uses more chips than other networks, it only uses one kind of chip. Implementation aspects of ATM switches